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2016年11月1日电院承办超威半导体(上海)有限公司宣讲会

[ 2016年10月14日 ]

举办方:电院

举办时间:2016年11月1日 18:30~21:00

举办地点:电信群楼3-100

单位名称:超威半导体(上海)有限公司

联系方式:董宇、15900507517、cosmo.dong@51job.com

专业要求:不限

学历要求:不限

宣讲会介绍:

 

 

 





 

 

 


关于AMD

AMD(NASDAQ: AMD)设计并集成尖端技术,为包括个人电脑、平板电脑、游戏机和云服务器等在内的数千万的智能设备提供强大动力,开启环绕计算的新时代。AMD解决方案让人们随时随地尽享其青睐的设备和应用的全部潜力,不断创造新的可能。

更多详情,敬请访问www.amd.com

 

 

About AMD

AMD (NASDAQ: AMD) designs and integrates technology that powers millions of intelligent devices, including personal computers, tablets, game consoles and cloud servers that define the new era of surround computing. AMD solutions enable people everywhere to realize the full potential of their favorite devices and applications to push the boundaries of what is possible. For more information, visit www.amd.com

 

 





 

 

 

 

 


职位

专业要

岗位职

ASIC Design Verification Engineer

EE, CS, or related

• Good understanding on ASIC design   verification flow
  • Programming knowledge on Verilog/SystemVerilog, C/C++
  • Knowledge on Perforce, OVL, SVA, SV, UVM, script programming etc.

Front-End Design Engineer

EE, CS, or related

• Familiar with EDA tools such as DC,   Formality, PT, CDC/LEDA                                                              • Regular run FEINT flow, check quality, drive/co-work IP team on   issue solving and QoR improvement
  • Develop RTL code for SoC top level and make sure functional correct

Physical Design Engineer

EE, CS, or related

• Familiar with general IC design flow,   familiar with physical design flow and EDA tool (Synopsys or Cadence) is a   plus.
  • Familiar with Linux, skill in scripts including perl/tcl/cshell/python is a   plus.
  • Good communication skills, proactive and team work.

ASIC Design implementation flow Engineer

EE, CS, or related

• Knowledge of ASIC design (Digital circuit   design, verilogHDL) is required
  • Be familiar with Linux working environment
  • Experience in program with one or more languages (CShell, TCL, Perl or   python etc.) is a plus

DFT Design Engineer

EE, CS, or related

• Implement DFT features including SCAN,   Boundary SCAN, MBIST, Analog Macro test logic and etc.
  • Generate DFT related timing constraints and work with PD team for timing   closure.
  • Participate in ATE bring-up and debug the DFT patterns on ATE.

Senior Software Development Engineer

EE, CS, SW, or related

• Work as part of the global Software   Customer Support engineering team to design and maintain the graphics device   driver and other software components
  • Resolve problem reports related to graphics device driver including   troubleshooting, debugging, & defect correction
  • Specify, design, and implement new ASIC and software features


  Graphics Driver Engineer

EE, CS, SW, or related

• Design, develop and debug kernel mode   driver, ISP driver, graphics driver, including DirectX/OpenGL/Vulkan drivers.
  • Work on supporting next generation Microsoft Windows,  Linux and Virtualization operation system
  • Work on bring up and support AMD next generation APU/GPU

BIOS Engineer

EE, CS, SW, or related

• Design, develop, and debug BIOS (System   Software) or UEFI Firmware for internal/external systems and platforms that   use AMD APU/CPU, AMD chipset, and 3rd party chipsets.
  • Participant in day-to-day BIOS development work using PC assembly and C   languages; will need to interact with internal organizations and customers.
  • Comfortable working with PC hardware and platform issues

Systems Design Engineer – Debug Engineer

EE, CS, or related

• Support new product bring-up and debug
  • Work with validation and cross functional teams providing support on   silicon related issues.
  • Create test procedures and generate technical documents as needed.

Systems Design Engineer – IPSE Engineer

EE, CS, or related

• Work closely with IP design team to   define IP validation test plan for both pre-silicon (emulation) and   post-silicon
  • Lead ASIC/ IP feature bring-up and validation, ensure coverage and schedule   will meet silicon tape-out date
  • Drive cross-team (ASIC design, platform, driver) collaboration to enable IP   features and optimize performance

 


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